Electronic component handlers receive numerous electronic components made for use in electronic circuits, present the electronic components to a test probe for parametric testing, and sort the electronic components according to the results of the parametric testing. One exemplary miniature electronic component suitable for handling and testing by an electronic component handler is a low inductance ceramic capacitor (LICC), which is a tiny rectangular “chip” that is smaller than a grain of rice. Additional exemplary electronic components suitable for handling and testing in an electronic component handler include integrated passive components (IPCs), capacitors chips, array chips, and resistors.
FIGS. 1 and 2 show an exemplary LICC or chip 10 that includes a body defined by a pair of first opposite side surfaces 12 (left and right surfaces), a pair of second opposite side surfaces 14 (upper and lower surfaces), and a pair of end surfaces 16 (front and back surfaces). The linear region that forms an edge of any of the surfaces (e.g., first opposite side, second opposite side, or end surfaces) is referred to as a “side margin.” Each of the first opposite side surfaces 12 has opposite side margins 18 shared in common with the side margins 20 of different ones of second opposite side surfaces 14. First opposite side surfaces 12 are spaced apart by a first distance (d1) defined by first opposite side margins 22 of end surfaces 16. Second opposite side surfaces 14 are spaced apart by a second distance (d2) defined by second opposite side margins 24 of end surfaces 16. Chip 10 also includes corner regions where three edges of any of the surfaces (e.g., first opposite side, second opposite side, or end surfaces) meet and form an angle. As is known to those of skill in the art, chip 10 may contain within its body multiple spaced-apart metal plates or may be a solid substrate. Chip 10 typically has a square or rectangular cross section.
Chip 10 further includes a first wraparound electrode 30 that wraps around each opposite side margin 18 in one of the pair of first opposite side surfaces 12. First wraparound electrode 30 forms first electrical contact regions 32 on second opposite side surfaces 14. Chip 10 further includes a second wraparound electrode 34 that wraps around each opposite side margin 18 of the other one of the pair of first opposite side surfaces 12. Second wraparound electrode 34 forms second electrical contact regions 36 on second opposite side surfaces 14.
First and second wraparound electrodes 30 and 34 are formed by application of an electrically conductive paste to chip 10. Great precision is needed when forming wraparound electrodes 30 and 34 to ensure that none of the conductive paste connects first and second electrical contact regions 32 and 36. Connection of opposed first and second wraparound electrodes 30 and 34 would form an electrically conductive bridge whose existence would cause the resulting chip 10 to become a short circuit. Consequently, first and second electrical contact regions 32 and 36 occupy only a minimal portion (e.g., about 15%) of each of second opposite side surfaces 14. There is no electrically conductive paste on either of opposite end surfaces 16.
Methods and apparatuses for testing and sorting large quantities of miniature electronic components, such as the LICC shown in FIGS. 1 and 2, are known in the art. One exemplary prior art method of and apparatus for testing and sorting electronic components is described in U.S. Pat. No. 6,204,464 (“the '464 patent”), which is owned by the assignee of the present patent application. FIGS. 3–7 show the overall arrangement of the physical elements of the prior art electronic component handler described in the '464 patent.
As shown in FIGS. 3 and 4, a high-speed electronic component handler 50 includes a rotatable feed wheel 52 that is mounted on a central shaft 54 and that rotates in a counterclockwise direction. Feed wheel 52 includes an outer rim 56 that is concentric with the axis (not shown) of central shaft 54. Feed wheel 52 is positioned at an angle, preferably 45°, to the horizontal and includes an upper surface 58 capable of receiving multiple, randomly oriented electronic components.
Feed wheel 52 includes multiple radially extending, spaced-apart bosses 66 that are uniformly angularly spaced along outer rim 56. Each boss 66 has a length sufficient to hold two or more chips 10 in a line and a width that is sufficiently narrow to admit each chip 10 only in an edge-wise orientation such that each chip 10 rests on one of its first or second opposite side surfaces 12 or 14 as it moves along the length of boss 66. In some embodiments, feed wheel 52 is subject to vibration that causes chips 10 that are placed on feed wheel 52 to enter boss 66.
FIG. 5 shows that as the length of boss 66 approaches outer rim 56, boss 66 turns downward about a chamfered or beveled corner 67 and terminates in an electronic component-sized cavity 68 that has no wall facing outward from outer rim 56. Each component-sized cavity 68 is configured to receive and hold within it a single chip 10 in a controlled orientation such that one of first or second opposite side surfaces 12 or 14 of chip 10 is exposed. Which one of first or second opposite side surfaces 12 or 14 is exposed depends solely on chance, as neither boss 66 nor electronic component-sized cavity 68 preferences which opposite side surface of chip 10 is exposed. A pressure differential created by a vacuum means 70, which is connected to a vacuum chamber 72, holds chip 10 in component-sized cavity 68 during rotation of feed wheel 52.
As shown in FIGS. 3, 6, and 7, a rotating carrier wheel 74 is mounted planar to, and spaced apart from, feed wheel 52 and is rotatable in a clockwise direction. Carrier wheel 74 is arranged in tangential adjacency with outer rim 56 of feed wheel 52 and includes an upwardly extending annular peripheral wall 76 that projects generally perpendicularly from a carrier plate 77. Peripheral wall 76 includes multiple spaced-apart test seats 78 that are uniformly angularly spaced around the periphery of carrier wheel 74. The rotation of carrier wheel 74 is coordinated with the rotation of feed wheel 52 to permit the transfer of chips 10 from feed wheel 52 to carrier wheel 74. More specifically, carrier wheel 74 and feed wheel 52 are rotated in synchronous peripheral velocity such that each test seat 78 is aligned with a component-sized cavity 68 when peripheral wall 76 of carrier wheel 74 and outer rim 56 of feed wheel 52 are in tangential adjacency. In this way, chips 10 in component-sized cavities 68 are transferred to test seats 78. As shown in FIG. 6, a pressure differential created by a second vacuum means 82 draws chips 10 out of component-sized cavities 68 into test seats 78, and a pressure differential created by a third vacuum means 84 holds chips 10 in test seats 78.
As shown in FIG. 7, each test seat 78 has a generally rectangular shape that includes a bottom surface 88 from which upwardly extends two side walls 90. When chip 10 is seated in test seat 78, one of the pair of end surfaces 16 of chip 10 rests upon and is supported by bottom surface 88. Either first opposite side surfaces 12 or second opposite side surfaces 14 are adjacent and generally parallel to side walls 90. Because test seat 78 does not include an outer wall, the other of first or second opposite side surfaces 12 or 14 is exposed.
FIGS. 8A and 8B are top views of chip 10 seated in test seat 78. FIG. 8A shows chip 10 seated in test seat 78 such that first opposite side surfaces 12 are exposed. When first opposite side surfaces 12 are exposed, first and second wraparound electrodes 30 and 34 are exposed, and parametric testing by a test probe 92 can be conducted on first and second wraparound electrodes 30 and 34. Exemplary parametric tests are described in U.S. Pat. No. 5,673,799 and include, but are not limited to, electrical, image, inspection, and visual testing. Testing is typically effected by electrically contacting one or both wraparound electrodes 30 and 34 of chip 10. Following testing, chips 10 are typically ejected from test seats 78 and sorted according to their test results.
FIG. 8B shows chip 10 seated in test seat 78 such that second opposite side surfaces 14 are exposed for contact by test probe 92. As such, first and second wraparound electrodes 30 and 34 are not exposed. Because parametric testing can only be conducted on wraparound electrodes 30 and 34, chip 10 of FIG. 8B cannot be parametrically tested. There is a 50% chance that chip 10 will be seated in test seat 78 with the orientation shown in FIG. 8B. Consequently, the prior art component handler shown in FIGS. 3–7 tests only half of the chips introduced into the handler. These prior art component handlers have significant system inefficiency that results in high manufacturing costs.
What is needed is an apparatus for and a method of seating an electronic component in an electronic component holder test seat such that it holds the electronic component in an orientation that exposes the electrodes of the electronic component to parametric testing.